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cat140xx ? 2006 catalyst semiconductor, inc. 1 doc. no. 1117 rev. a characteristics subject to change without notice voltage supervisor with i 2 c serial cmos eeprom features ? precision power supply voltage monitor ? 5v, 3.3v, 3v & 2.5v systems ? 7 threshold voltage options ? active high or low reset ? valid reset guaranteed at v cc = 1 v ? supports standard and fast i 2 c protocol ? 16-byte page write buffer ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial temperature range ? rohs-compliant 8-pin soic package for ordering information details, see page 14. pin configuration description the cat140xx (see table below) are memory and supervisory solutions for mi crocontroller based systems. a cmos serial eeprom memo ry and a system power supervisor with brown-out protection are integrated together. memory interface is via both the standard (100khz) as well as fast (400khz) i 2 c protocol. the cat140xx provides a precision v cc sense circuit with two reset output options: cmos active low output or cmos active high. the reset output is active whenever v cc is below the reset threshold or falls below the reset threshold voltage. the power supply monitor and reset circuit protect system controllers during power up/down and against brownout conditions. seven reset threshold voltages support 5v, 3.3v, 3v and 2.5v systems. if power supply voltages are out of tolerance reset signals become active, preventing t he system microcontroller, asic or peripherals from operating. reset signals become inactive typically 240ms after the supply voltage exceeds the reset threshold level. memory size selector product memory density 14002 2-kbit 14004 4-kbit 14008 8-kbit 14016 16-kbit pin function pin name function a0, a1, a2 device address inputs sda serial data input/output scl serial clock input rst/ rst reset output v cc power supply v ss ground nc no connect threshold suffix selector nominal threshold voltage threshold suffix designation 4.63v l 4.38v m 4.00v j 3.08v t 2.93v s 2.63v r 2.32v z 8 7 6 5 v cc rst/rst scl sda nc / nc / nc / nc / a 0 cat14016 / 08 / 04 / 02 soic (w) nc / nc / a 1 a 1 1 2 3 4 a 2 a 2 a 2 v ss / / /
cat140xx doc. no. 1117 rev. a 2 ? 2006 catalyst semiconductor, inc. characteristics subject to change without notice block diagram absolute maximum ratings (1) parameters ratings units storage temperature -65 to +150 c voltage on any pin with respect to ground (2) -0.5 to +6.5 v reliability characteristics (3) symbol parameter min units nend (4) endurance 1,000,000 program/ erase cycles tdr data retention 100 years d.c. operating characteristics v cc = +2.5v to +5.5v unless otherwise specified. limits symbol parameter min. typ. max. test condition units i cc supply current 1 read or write at 400khz ma 10 22 v cc < 5.5v; all i/o pins at v ss or v cc i sb standby current 8 17 v cc < 3.6v; all i/o pins at v ss or v cc a i l i/o pin leakage 2 pin at gnd or v cc a v il input low voltage -0.5 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage sda 0.4 v cc 2.5 v, i ol = 3.0 ma v notes: (1) stresses above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. these are stress ra tings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sectio ns of this specification is not implied. exposure to any absolute maximum rating for extended pe riods may affect device performance and re liability. (2) the dc input voltage on any pin should not be lower than -0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than -1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. (3) these parameters are tested initially and after a design or process change that affects the parameter according to appropr iate aec-q100 and jedec test methods. (4) page mode, v cc = 5 v, 25c sda eeprom scl a0 a1 a2 v cc voltage detector rst or rs t v ss
cat140xx ? 2006 catalyst semiconductor, inc. 3 doc. no. 1117 rev. a characteristics subject to change without notice a.c. characteristics (memory) (1) v cc = 2.5v to 5.5v, t a = -40c to 85c, unless otherwise specified. standard fast symbol parameter min max min max units f scl clock frequency 100 400 khz t hd:sta start condition hold time 4 0.6 s t low low period of scl clock 4.7 1.3 s t high high period of scl clock 4 0.6 s t su:sta start condition setup time 4.7 0.6 s t hd:dat data in hold time 0 0 s t su:dat data in setup time 250 100 ns t r (2) sda and scl rise time 1000 300 ns t f (2) sda and scl fall time 300 300 ns t su:sto stop condition setup time 4 0.6 s t buf bus free time between stop and start 4.7 1.3 s t aa scl low to data out valid 3.5 0.9 s t dh data out hold time 100 100 ns t i (2) noise pulse filtered at scl and sda inputs 100 100 ns t wr write cycle time 5 5 ms t pu (2, 3) power-up to ready mode 1 1 ms notes : (1) test conditions according to ?a.c. test conditions? table. (2) tested initially and after a design or pr ocess change that affects this parameter. (3) t pu is the delay between the time v cc is stable and the device is ready to accept commands. a.c. test conditions input levels 0.2 x v cc to 0.8 x v cc input rise and fall times 50 ns input reference levels 0.3 x v cc , 0.7 x v cc output reference levels 0.5 x v cc output load current source: i ol = 3 ma; c l = 100 pf
cat140xx doc. no. 1117 rev. a 4 ? 2006 catalyst semiconductor, inc. characteristics subject to change without notice electrical characteristic s (supervisory function) v cc = full range, t a = -40oc to +85oc unless otherw ise noted. typical values at t a = +25oc and v cc = 5v for l/m/j versions, v cc = 3.3v for t/s versions, v cc = 3v for r version and v cc = 2.5v for z version. symbol parameter threshold conditions min typ max units t a = +25oc 4.56 4.63 4.70 l t a = -40oc to +85oc 4.50 4.75 t a = +25oc 4.31 4.38 4.45 m t a = -40oc to +85oc 4.25 4.50 t a = +25oc 3.93 4.00 4.06 j t a = -40oc to +85oc 3.89 4.10 t a = +25oc 3.04 3.08 3.11 t t a = -40oc to +85oc 3.00 3.15 t a = +25oc 2.89 2.93 2.96 s t a = -40oc to +85oc 2.85 3.00 t a = +25oc 2.59 2.63 2.66 r t a = -40oc to +85oc 2.55 2.70 t a = +25oc 2.28 2.32 2.35 v th reset threshold voltage z t a = -40oc to +85oc 2.25 2.38 v symbol parameter conditions min typ (1) max units reset threshold tempco 30 ppm/oc t rpd v cc to reset delay (2) v cc = v th to (v th -100mv) 20 s t purst reset active timeout period t a = -40oc to +85oc 140 240 460 ms v cc = v th min, i sink = 1.2 ma r/s/t/z 0.3 v cc = v th min, i sink = 3.2 ma j/l/m 0.4 v ol reset output voltage low (push-pull, active low, cat140xx9) v cc > 1.0v, i sink = 50a 0.3 v v cc = v th max, i source = -500a r/s/t/z 0.8v cc v oh reset output voltage high (push-pull, active low, cat140xx9) v cc = v th max, i source = -800a j/l/m v cc - 1.5 v v cc > v th max, i sink = 1.2ma r/s/t/z 0.3 v ol reset output voltage low (push-pull, active high, cat140xx1) v cc > v th max, i sink = 3.2ma j/l/m 0.4 v v oh reset output voltage high (push-pull, active high, cat140xx1) 1.8v < v cc v th min, i source = -150a 0.8v cc v notes : (1) production testing done at t a = +25oc; limits over temperature guaranteed by design only. (2) reset output for the cat140xx9; reset output for the cat140xx1.
cat140xx ? 2006 catalyst semiconductor, inc. 5 doc. no. 1117 rev. a characteristics subject to change without notice pin description reset/ reset : reset output this output is available in two versions: cmos active low (cat140xx9) and cmos active high (cat140xx1). both versions are push-pull outputs for high efficiency. sda: serial data address the serial data i/o pin receives input data and transmits data stored in eeprom. in transmit mode, this pin is open drain. data is acquired on the positive edge, and is delivered on the negative edge of scl. scl: serial clock the serial clock input pin accepts the serial clock generated by the master. a0, a1, a2: device address inputs the address inputs set the device address when cascading multiple devices. when not driven, these pins are pulled low internally. device operation the cat140xx products combine the accurate voltage monitoring capabilities of a standalone voltage supervisor with the high quality and reliability of standard eeproms from catalyst semiconductor. reset controller description the reset signal is asserted low for the cat140xx9 and high for the cat140xx1 when the power supply voltage falls below the threshold trip voltage and remains asserted for at least 140ms (t purst ) after the power supply voltage has risen above the threshold. reset output timing is shown in figure 1. the cat140xx devices protect ps against brownout failure. short duration v cc transients of 4 sec or less and 100mv amplitude typically do not generate a reset pulse. figure 2 shows the maximum pulse duration of negative- going v cc transients that do not cause a reset condition. as the amplitude of the transient goes further below the threshold (increasing v th - v cc ), the maximum pulse duration decreases. in this test, the v cc starts from an initial voltage of 0.5v above the threshold and drops below it by the amplit ude of the overdrive voltage (v th - v cc ). figure 2. maximum transient duration without causing a reset pulse vs. overdrive voltage fi g ure 1. reset output timin g transie n t du r ation [s] reset overdrive v th - v cc [mv] t amb = 25oc cat140xxm cat140xxz v cc purst t purst t rpd t rvalid v v th rese t rese t cat140xx9 cat140xx1 rpd t
cat140xx doc. no. 1117 rev. a 6 ? 2006 catalyst semiconductor, inc. characteristics subject to change without notice embedded eeprom operation the cat140xx supports the inter-integrated circuit (i 2 c) bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. data flow is controlled by a master device, which generates the serial clock and all start and stop conditions. the cat140xx acts as a slave device. master and slave alternate as either transmitter or receiver. i 2 c bus protocol the i 2 c bus consists of two ?wires?, scl and sda. the two wires are connected to the v cc supply via pull-up resistors. master and slave devices connect to the 2-wire bus via their respective scl and sda pins. the transmitting device pulls down the sda line to ?transmit? a ?0? and releases it to ?transmit? a ?1?. data transfer may be initiated only when the bus is not busy (see a.c. characteristics). during data transfer, the sda line must remain stable while the scl line is high. an sda transition while scl is high will be interp reted as a start or stop condition (figure 3). the start condition precedes all commands. it consists of a high to low transition on sda while scl is high. the start acts as a ?wake-up? call to all receivers. absent a start, a slave will not respond to commands. the stop condition completes all commands. it consists of a low to high transition on sda while scl is high. start the start condition precedes all commands. it consists of a high to low transition on sda while scl is high. the start acts as a ?wake-up? call to all receivers. absent a start, a slave will not respond to commands. stop the stop condition completes all commands. it consists of a low to high transition on sda while scl is high. the stop starts the internal write cycle (when following a write command) or sends the slave into standby mode (when following a read command). device addressing the master initiates data transfer by creating a start condition on the bus. the master then broadcasts an 8-bit serial slave address. for normal read/write operations, the first 4 bits of the slave address are fixed at 1010 (a h). the next 3 bits are used as programmable address bits when cascading multiple devices and/or as internal address bits. the last bit of the slave address, r/ w , specifies whether a read (1) or write (0) operation is to be performed. the 3 address space extension bits are assigned as illustrated in figure 4. a 2 , a 1 and a 0 must match the state of the external address pins, and a 10 , a 9 and a 8 are internal address bits. acknowledge after processing the slave address, the slave responds with an acknow ledge (ack) by pulling down the sda line during the 9 th clock cycle (figure 5). the slave will also acknowledge the address byte and every data byte presented in write mode. in read mode the slave shifts out a data byte, and then releases the sda line during the 9 th clock cycle. as long as the master acknowledges the data, the slave will continue transmitting. the master terminates the session by not acknowledgi ng the last data byte (noack) and by issuing a stop condition. bus timing is illustrated in figure 6.
cat140xx ? 2006 catalyst semiconductor, inc. 7 doc. no. 1117 rev. a characteristics subject to change without notice figure 3. start/stop conditions figure 4. slave address bits figure 5. acknowledge timing figure 6. bus timing start condition stop condition sda scl 1010 a 10 a 9 a 8 r/w cat14016 1010 a 2 a 9 a 8 r/w cat14008 1010 a 2 a 1 a 8 r/w cat14004 1010 a 2 a 1 a 0 r/w CAT14002 189 start scl from master bus release delay (transmitter) bus release delay (receiver) data output from transmitter data output from receiver ack delay ( t aa ) ack setup ( t su:dat ) t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh
cat140xx doc. no. 1117 rev. a 8 ? 2006 catalyst semiconductor, inc. characteristics subject to change without notice write operations byte write in byte write mode, the master sends the start condition and the slave address with the r/ w bit set to zero to the slave. after the slave generates an acknowledge, the master send s the byte address that is to be written into the address pointer of the cat140xx. after receiving another acknowledge from the slave, the master transmits the data byte to be written into the addressed memory location. the cat140xx device will acknowledge the data byte and the master generates the stop condition, at which time the device begins its internal write cycle to nonvolatile memory (figure 7). while this internal cycle is in progress (t wr ), the sda output will be tri- stated and the cat140xx w ill not respond to any request from the master device (figure 8). page write the cat140xx writes up to 16 bytes of data in a single write cycle, using the page write operation (figure 9). the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the data byte is transmitted, the master is allowed to send up to fifteen additional bytes. after each byte has been transmitted the cat140xx will respond with an acknowledge and internally increments the f our low order address bits. the high order bits that define the page address remain unchanged. if the master transmits more than sixteen bytes prior to sending the stop condition, the address counter ?wraps around? to the beginning of page and previously transmitted data will be overwritten. once all si xteen bytes are received and the stop condition has been sent by the master, the internal write cycle begins. at this point all received data is written to the cat140xx in a single write cycle. acknowledge polling the acknowledge (ack) polling routine can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host?s write operat ion, the cat140xx initiates the internal write cycle. the ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the cat140xx is still busy with the write operation, noack will be returned. if the cat140xx has completed the internal write operation, an ack will be returned and the host can then proceed with the next read or write operation.
cat140xx ? 2006 catalyst semiconductor, inc. 9 doc. no. 1117 rev. a characteristics subject to change without notice figure 7. byte write sequence figure 8. write cycle timing figure 9. page write timing address byte data byte slave address s a c k a c k a c k s t o p p s t a r t bus activity: master slave a 7 ? a 0 d 7 d 0 t wr stop condition start condition address ack 8 th bit byte n scl sda a c k a c k a c k s t o p s a c k a c k s t a r t p slave address n = 1 p 15 address byte data byte n data byte n+1 data byte n+p bus activity: master slave
cat140xx ? 2006 catalyst semiconductor, inc. 10 doc. no. 1117 rev. a characteristics subject to change without notice read operations immediate read upon receiving a slave address with the r/ w bit set to ?1?, the cat140xx will inte rpret this as a request for data residing at the current byte address in memory. the cat140xx will acknowledge the slave address, will immediately shift out the data residing at the current address, and will then wait for the master to respond. if the master does not acknowledge the data (noack) and then follows up with a stop condition (figure 10), the cat140xx returns to standby mode. selective read selective read operations allow the master device to select at random any memory location for a read operation. the master device first performs a ?dummy? write operation by sending the start condition, slave address and byte address of the location it wishes to read. after the cat140xx acknowledges the byte address, the master device resends the start condition and the slave address, this time with the r/ w bit set to one. the cat140xx then responds with its acknowledge and sends the requested data byte. the master device does not ac knowledge the data (noack) but will generate a stop condition (figure 11). sequential read if during a read session, the master acknowledges the 1 st data byte, then the cat140xx will continue transmitting data residing at subsequent locations until the master responds with a noack, followed by a stop (figure 12). in contrast to page write, during sequential read the address co unt will automatically increment to and then wrap-around at end of memory (rather than end of page). power-on reset (por) each cat140xx incorporates power-on reset (por) circuitry which protects the internal logic against powering up in the wrong state. a cat140xx device will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi-directional por feature protects the device against ?brown-out? failure follo? wing a temporary loss of power. delivery state the cat140xx is shipped erased, i.e., all bytes are ffh.
cat140xx ? 2006 catalyst semiconductor, inc. 11 doc. no. 1117 rev. a characteristics subject to change without notice figure 10. immediate read sequence and timing figure 11. selective read sequence figure 12. sequential read sequence scl sda 8 th bit stop no ack data out 89 slave address s a c k data byte n o a c k s t o p p s t a r t bus activity: master slave slave s a c k n o a c k s t o p p s t a r t s a c k slave address a c k s t a r t data byte address byte address bus activity: master slave a c k a c k a c k s t o p n o a c k a c k p slave address data byte n data byte n+1 data byte n+2 data byte n+x bus activity: master slave
cat140xx doc. no. 1117 rev. a 12 ? 2006 catalyst semiconductor, inc. characteristics subject to change without notice package outlines 8-lead 150 mil soic (w) notes: (1) all dimensions are in millimeters. (2) complies with jedec specification ms-012 dimensions. symbol a1 a b c d e e1 h l min 0.10 1.35 0.33 4.80 5.80 3.80 0.25 0.40 nom 0.25 0.19 max 0.25 1.75 0.51 5.00 6.20 4.00 e 1.27 bsc 0.50 1.27 q1 0 8 e e1 d a1 e l q1 c b h x 45 a for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat140xx ? 2006 catalyst semiconductor, inc. 13 doc. no. 1117 rev. a characteristics subject to change without notice ordering information notes: (1) all packages are rohs-comp liant (lead-free, halogen-free). (2) the standard lead finish is nipd au pre-plated (ppf) lead frames. (3) the device used in the above example is a CAT140029swi-gt3 (2kb eeprom, with active low cmos output, with a reset threshold between 2.85v - 3.00v, in an soic, industrial temperature, nipdau, tape and reel. (4) for additional package and temperature options, please contact your nearest ca talyst semiconductor sales office. prefix device # suffix cat 14002 9 s w i - g t3 company id package w: soic reset threshold voltage l: 4.50v ? 4.75v m: 4.25v ? 4.50v j: 3.89v ? 4.10v t: 3.00v ? 3.15v s: 2.85v ? 3.00v r: 2.55v ? 2.70v z: 2.25v ? 2.38v lead finish g: nipdau (ppf) temperature range i = industrial (-40oc to 85oc) product type with memory density 02 ? 2k-bits 04 ? 4k-bits 08 ? 8k-bits 16 ? 16k-bits supervisor output type 9: cmos active low 1: cmos active high tape & reel t: tape & reel 3: 3000 units / reel
revision history date rev. reason 11/09/06 a initial issue copyrights, trademarks and patents trademarks and register ed trademarks of catalyst semiconductor include each of the following: beyond memory?, dpp?, ezdim?, minipot?, and quad-mode? catalyst semiconductor has been issued u. s. and foreign patents and has patent applicat ions pending that protect its products. catalyst semiconductor makes no warranty, representation or gu arantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its pro ducts will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any ot her application in which the failure of the catalyst semiconduct or product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or se rvice described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in pr oduction or offered for sale. catalyst semiconductor advises customers to obtain the current version of the rele vant product informati on before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 document no: 1117 fax: 408.542.1200 revision: a www.catsemi.com issue date: 11 / 09 / 06

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